The disclosed invention is directed generally to synchronous digital circuit performance monitoring circuits, and more particularly to circuits for monitoring speed performance degradation in synchronous digital integrated circuits.
During the lifetime of a digital integrated circuit, its speed performance varies due to changing environmental conditions and aging. Speed of operation (i.e., clocking rate) of digital integrated circuits is typically based on worst case design parameters whereby a digital integrated circuit is clocked at a rate that will provide proper operation at the worst case condition. If a digital integrated circuit should operate outside its worst case design point, the system in which it operates will fail.
There are basically two types of speed failures: setup failure which occurs when the input data to a flip-flop is not stable for a predetermined amount of time prior to the active clock transition, and hold time failure which occurs when the input data to a flip-flop is not stable for a predetermined amount of time after the active clock transition.
Presently, proper speed operation of synchronous digital integrated circuits can be verified by running tests. Set-up time margins can be evaluated by increasing clock frequency to set-up failure, and then comparing that frequency to the desired operating frequencies. However, set-up margin cannot be evaluated during actual in-system operation. Hold-time margin cannot be measured at all, since hold time margin is independent of clock frequency, and any test as to hold time can only provide a pass/fail indication.
It would be desirable to not only test for speed, but also to assure that finite speed margins exist in a design. Speed margins are an extra increment of speed performance in devices over what is used in system. For example, sufficient set up margin might be designed so that the digital integrated circuits could clock 10% faster than the system clock rate; sufficient hold time margin might be designed so that data would be held at flip-flop inputs 10% longer than required. The use of margins is sound design practice that assures reliable operation over the lifetime of a digital system.